Design-for-Test Optimization for Low-Power Semiconductor Devices: A Survey

Abstract

A big design challenge for semiconductor devices is power consumption during testing, since these devices are getting smaller while getting more complicated and having more integration density. If the tests are to be economical, scalable, and dependable without sacrificing performance or adding extra system costs, it need to optimize the Design-for-Test for low power consumption. This survey provides an in-depth analysis of important low-power DFT approaches, such as clock gating, scan chain reordering, Built-In Self-Test (BIST), and test data compression, with the goal of minimizing static and dynamic power consumption during testing. In order to manage switching activity, leakage currents, and enable complicated System-on-Chip (SoC) architectures, power-aware DFT is crucial. The evolution of BIST architectures and the use of low-power test controllers in portable and high-performance systems are discussed in detail. Additionally, the impact of semiconductor scaling, multi-voltage domains, and advanced packaging technologies on test strategies is explored. Emerging trends such as AI-driven test generation and adaptive power control offer promising directions for sustainable and intelligent test solutions. These strategies not only enhance test efficiency and coverage but also contribute to reducing thermal stress, extending device lifespan, and supporting green design initiatives in modern semiconductor development.