Energy-Aware Mobile Processor Architectures: A Systematic Review of Design Principles and Optimization Methods

Abstract

The increasing need for high-performance and high-energy efficiency in mobile computing has resulted in significant innovations in mobile processor architectures. This review article examines some of the major design concepts and algorithm optimization techniques that can be used to ensure energy efficiency and computational power balance in mobile devices. It explores such architectural innovations as RISC-V, logic-memory co-integration, and system-level technologies as clock gating, power gating, and dynamic voltage and frequency scaling (DVFS). Moreover, the paper also discusses software-hardware co-design options, thermal-aware scheduling, and the new machine learning-based energy prediction and management approaches. This study gives us an idea of the dynamic nature of mobile processor design to enhance performance with longer battery life through synthesis of the existing research and developments. The findings are especially applicable because mobile applications are becoming increasingly more demanding with regard to computation. The mentioned techniques can be considered the basis of future innovation in the cellular energy optimization and chip architecture.